Keyloh
Research direction

Descent.

Keyloh is researching a spatio-temporal chiplet architecture that combines specialised logic, memory-adjacent computation, and software-directed workload scheduling.

This is the research programme beneath the Telos platform, pursued so that the economics of local intelligence improve with every generation — and so the direction of the company rests on foundations it owns.

Exploratory render of a chiplet package, exploded into layers: memory stacks, compute chiplets, and package substrate.
Architecture concept — exploratory, not final silicon

Visualisations on this page represent exploratory architecture studies and may not reflect the final implementation, packaging, specifications, or production design. Detailed engineering material is shared through the technical brief after qualification.

Silicon is where the economics compound.

Systems establish the position. Software makes them useful. Silicon is the layer that makes both cheaper, faster, and more capable with every generation.

Descent is a first-principles research programme with one job in view: running the largest models close to the people who use them, at a cost per deployed capability the centralised model cannot follow. The programme is staged and disciplined — each step committed only when the one before it has earned it.

Beyond Keyloh’s own systems, the work opens commercial pathways in design services, IP licensing, and components.

Research direction

Compute belongs beside memory.

In modern inference, moving data costs more than computing with it. Most of an accelerator’s energy and time is spent carrying weights and activations between distant memory and hungry logic.

Descent starts from that observation and inverts it: put computation next to the memory that feeds it, and move data millimetres instead of centimetres. Dedicated memory-compute chiplets sit adjacent to specialised logic chiplets, interleaved across the package so no tensor travels further than it must.

The result Keyloh is working toward is simple to state and hard to do: less data movement, higher utilisation, and economics that improve with every generation.

The architecture at a glance

One package, disaggregated into the parts intelligence actually needs — then converged on one address space and one runtime.

Annotated exploded view of an exploratory chiplet package showing memory tiers, compute chiplets, interconnect, and substrate. 01 02 03 04 05
  1. 01High-bandwidth memory tier. Model weights live in stacked memory, streamed on demand.
  2. 02Memory-adjacent compute. SRAM-tier chiplets that compute where the hot data already is.
  3. 03Specialised logic chiplets. Dense engines shaped for the workloads of modern models.
  4. 04Package-scale interconnect. Data moves the shortest distance that can serve it.
  5. 05One package, one address space. The parts behave as a single machine to the software above.

Illustrative concept — component arrangement is indicative, not a floorplan.

Research direction

Two memory tiers, one pool.

The architecture pairs a fast SRAM tier — computing directly against the data it holds — with a high-bandwidth memory tier that streams model weights as they are needed. Software sees neither seam: a unified pool, one address space.

Keeping the hot working set — activations, caches, the state a model touches every step — beside compute is where the architecture earns its name: the memory is folded into the computation rather than standing apart from it.

Research visualisation of a metal-stack study: routing layers rendered above standard-cell rows.
Metal-stack study — research visualisation
Research direction

Folded in space, folded in time.

The programme’s name for the idea is spatio-temporal folding — using both dimensions the hardware has.

  1. Spatial folding

    The machine is partitioned into chiplets so that memory and the logic that consumes it sit side by side, interleaved across the package — shortening every journey a tensor makes.

  2. Temporal folding

    Software-directed scheduling packs work into every clock cycle — overlapping the distinct phases of inference so no engine waits idle while another finishes.

  3. Hardware and software, co-designed

    The scheduler is designed with the silicon, not after it — the same discipline that shapes Keyloh AI OS and the Telos runtime shapes how the architecture spends its cycles.

  4. Utilisation as the measure

    The goal across every inference stage is the same: hardware that works as hard on its quietest cycle as its busiest — because utilisation, not peak numbers, is what owners actually pay for.

Disaggregated, then converged

Most silicon forces a choice: general-purpose flexibility or specialised speed. Descent explores taking the machine apart — and converging the parts on one package, one address space, one runtime.

  1. General-purpose compute, on package

    A compute complex beside the accelerator, so a system can run its own OS, runtime, and orchestration without an external host.

  2. Specialised acceleration

    Dense engines built for the shapes of modern models — inference and on-device fine-tuning as first-class workloads.

  3. A reconfigurable fabric

    Adaptable logic alongside the fixed engines, so the same silicon can take on custom operators and emerging model families.

  4. The Network-on-Package

    A locality-first interconnect binding compute, acceleration, fabric, and memory into one machine — without global coherence overhead.

The studies so far

Keyloh’s silicon research has progressed through multiple architectural studies — exploring chiplet partitioning, memory proximity, interconnect topology, and workload scheduling. A selection, shared as they are: exploration, not product.

Early chiplet study: a symmetric die layout visualisation with repeated compute and memory blocks.
Early chiplet study — die-level partitioning
Layered stack study: routing and cell layers of a die rendered as separated planes.
Layered stack study — research visualisation
Architectural study of an alternative die organisation.
Previous architecture iteration
Architectural study exploring a different balance of memory and logic.
Exploratory silicon design — memory-to-logic balance
Concept render of a delidded package with a central die and four memory stacks.
Package concept — illustrative, not final silicon
Exploratory accelerator board study drawn as a white engineering blueprint.
Exploratory accelerator board study

From commercial silicon to our own.

In development
Telos systems are being developed on commercially available accelerator and memory technologies — the practical path to putting locally held intelligence to work now. About the systems →
Research direction
Descent explores the proprietary architecture those systems could stand on: chiplet-based acceleration, memory-adjacent computation, and software-directed temporal scheduling.

The sequence is deliberate. Ship on what exists; research what should exist; and let each generation of the second improve the economics of the first.

One package, one address space, one runtime.

Research visualisation — exploratory architecture study

The technical brief

Engineering detail — architecture, interfaces, and validation status — is shared through a controlled technical brief for qualified investors, semiconductor partners, and enterprise customers. Sensitive material is released after qualification and, where justified, under NDA.

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What we publish here is the thesis. What we build from it is shared in person.